69th Annual IEEE International Electron Devices Meeting

Date : 9th December 2023 to 13th December 2023

Place : United States of America, San Francisco

Website :https://www.ieee.org/

Contact Person:IEEE

Description:

ADVANCED LOGIC TECHNOLOGY (ALT) Papers are solicited in the areas of CMOS platform technologies and applications (e.g., HPC, LOP, mobile, automotive, low-temperature CMOS, etc.), logic devices and circuits, process integration schemes for advanced nodes, innovations in material, process and metrology techniques, and design technology co-optimization (DTCO) and system technology co-optimization (STCO). Platform technologies include state-of-the-art Si and beyond-Si channel devices, gate-all-around devices, stacked devices with different polarity transistors, advanced interconnect, novel power distribution integration schemes, heterogenous 2.5D/3D integration schemes, and BEOL compatible transistors. Device architecture, device design and analysis, process integration, module advancements in process and patterning, metrology, physical layout effects, techniques for reduced variability, yield, methodologies and solutions for DTCO/STCO in the solicited areas are of high interest.

69th Annual IEEE International Electron Devices Meeting will be held in San Francisco,United States of America on date 2023-12-13

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Deadline for abstracts/proposals : 13th July 2023

Keynote Speakers :

Venue :San Francisco, CA, USA

Check the event website for more details.