Place : United States of America, San Francisco
Description:Papers are solicited in the areas of CMOS platform technologies and applications (e.g., HPC, LOP, mobile, automotive, low-temperature CMOS, etc.), logic devices and circuits, process integration schemes for advanced nodes, innovations in material, process and metrology techniques, and design technology co-optimization (DTCO) and system technology co-optimization (STCO). Platform technologies include state-of-the-art Si and beyond-Si channel devices, gate-all-around devices, stacked devices with different polarity transistors, advanced interconnect, novel power distribution integration schemes, heterogenous 2.5D/3D integration schemes, and BEOL compatible transistors. Device architecture, device design and analysis, process integration, module advancements in process and patterning, metrology, physical layout effects, techniques for reduced variability, yield, methodologies and solutions for DTCO/STCO in the solicited areas are of high interest. EMERGING DEVICE and COMPUTE TECHNOLOGY (EDT) Papers are solicited on emerging nanoelectronic devices and physics. This includes devices based on novel transport and control mechanisms such as tunnel FET, negative capacitance FET, topological materials and devices, phase transitions, ferroelectrics and quantum effects. Devices based on lowâ€dimensional systems including 2D materials, CNTs, nanowires, and quantum dots are welcomed. Devices with novel device functions and/or novel materials for neuromorphic compute, approximate and analog compute, and non-charge-based compute such as spintronics are key topics. Furthermore, emerging state machines and time dynamical compute systems are also of interest. Qubit devices as well as devices and systems designed to enable quantum computing, quantum simulation and quantum annealing are of high interest. Papers in EDT focus primarily on device physics, innovative transistor structures, and novel concepts; more mature â€œplatform candidateâ€ papers, such as based on established two-terminal resistive memories, should be submitted to ALT and MT. Reliability assessment of emerging devices are also solicited here, while assessments for more mature devices should be submitted to RSD.
Deadline for abstracts/proposals : 13th July 2023
Organized By :admin
Keynote Speakers :
Venue :San Francisco, CA, USA
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